cpu0 is sacred

This is the layout the machine ended up with:

cpu0 ──── PPS interrupt.  Nothing else. Ever.
cpu1 ──── web tier (dashboard, Caddy)
cpu2 ──── chronyd     (isolated)
cpu3 ──── gpsd + UART IRQ thread   (isolated)

Not one of those four lines came from a guide. Each came from a measurement that contradicted an assumption.

• cpu0 holds the PPS interrupt because the Pi 4’s GPIO mux physically refuses to move it. That isn’t a preference; it’s a constraint we cannot configure away.
• cpu2 and cpu3 are isolated (isolcpus=2,3) for the timing daemons, which want determinism more than throughput.
• cpu1 got the web tier only after a benchmark caught it taxing the clock 36% from cpu0.

The rule this implies

Because the PPS interrupt cannot be relocated, cpu0 is load-bearing for precision in a way no other core is. Anything you schedule there is competing directly with the timestamp.

So: every service on this box — an exporter, a log shipper, a backup job, a cron entry, anything you add six months from now — belongs on cpu1–3.

[Service]
CPUAffinity=1
Nice=10

It’s a one-line tax, and the alternative is a slow, invisible erosion of the one number the machine exists to produce.

Isolation alone did nothing

Worth saying plainly: isolcpus on its own did not improve PPS jitter, and plausibly made it worse — by evacuating cpu2/3, we concentrated everything else onto cpu0/1, which is where the PPS interrupt lives. Isolation only pays once you also keep the evacuated work away from the PPS core.